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White Electronic Designs
WV3DG7266V-D1
PRELIMINARY*
512MB - 2x32Mx72 SDRAM, UNBUFFERED, w/PLL
FEATURES
PC100 and PC133 Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V 0.3V Power Supply Dual Rank 144 Pin SO-DIMM JEDEC * PCB: 31.75mm (1.25")
* This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
DESCRIPTION
The WV3DG7266V is a 2x32Mx72 synchronous DRAM module which consists of nine stacked 64Mx8 with 4 banks SDRAM components in TSOP II package, and one 2Kb EEPROM for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate.
PIN NAMES
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT PIN FRONT PIN 1 VSS 2 3 DQ0 4 5 DQ1 6 7 DQ2 8 9 DQ3 10 11 VCC 12 13 DQ4 14 15 DQ5 16 17 DQ6 18 19 DQ7 20 21 VSS 22 23 DQM0 24 25 DQM1 26 27 VCC 28 29 A0 30 31 A1 32 33 A2 34 35 VSS 36 37 DQ8 38 39 DQ9 40 41 DQ10 42 43 DQ11 44 45 VCC 46 47 DQ12 48
August 2005 Rev. 1
BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44
PIN FRONT PIN 49 DQ13 50 51 DQ14 52 53 DQ15 54 55 VSS 56 57 CB0 58 59 CB1 60 61 CLK0 62 63 VCC 64 65 RAS# 66 67 WE# 68 69 CS0# 70 71 CS1#* 72 73 NC 74 75 VSS 76 77 CB2 78 79 CB3 80 81 VCC 82 83 DQ16 84 85 DQ17 86 87 DQ18 88 89 DQ19 90 91 VSS 92 93 DQ20 94 95 DQ21 96
BACK DQ45 DQ46 DQ47 VSS CB4 CB5 CKE0 VCC CAS# CKE1 A12 NC CLK1 VSS CB6 CB7 VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53
PIN FRONT PIN 97 DQ22 98 99 DQ23 100 101 VCC 102 103 A6 104 105 A8 106 107 VSS 108 109 A9 110 111 A10 112 113 VCC 114 115 DQM2 116 117 DQM3 118 119 VSS 120 121 DQ24 122 123 DQ25 124 125 DQ26 126 127 DQ27 128 129 VCC 130 131 DQ28 132 133 DQ29 134 135 DQ30 136 137 DQ31 138 139 VSS 140 141 SDA 142 143 VCC 144
1
BACK DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
A0 - A12 BA0-1 DQ0-63 CLK0, CLK1 CB0-7 CKE0 CS0#, CS1# RAS# CAS# WE# DQM0-7 VCC VSS SDA SCL DNU NC
Address Input (Multiplexed) Select Bank Data Input/Output Clock Input Check Bit (Data-In/Data-Out) Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe #Write Enable DQM Power Supply (3.3V) Ground Serial Data I/O Serial Clock Do Not Use No Connect
* These pins are not used in this module ** These pins should be NC in the system which does not support SPD.
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FUNCTIONAL BLOCK DIAGRAM
CS1# CS0# DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0-A12 BA0-BA1 RAS# CAS# CKE0 WE# CS0# CS1# VCC DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A0-A12: SDRAM BA0-BA1: SDRAM RAS#: SDRAM CAS#: SDRAM CKE0: SDRAM WE#: SDRAM CS0#: SDRAM CS1#: SDRAM SDRAM 10 VSS SDRAM Two 0.1uf capacitors per each SDRAM
DQn
WV3DG7266V-D1
PRELIMINARY
DQM4 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS#
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS#
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS#
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS#
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS#
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS#
DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS#
CS#
10
CLK0
12pF
PLL CLOCK DRIVER
10pF
CK0
10
CLK1 10pF
Serial PD SCL SDA
A0 A1
A2
Every DQPin of SDRAM
August 2005 Rev. 1
2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6
WV3DG7266V-D1
PRELIMINARY
Units V V C W mA
-55 ~ +150 18 50
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0C TA +70C Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ +0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH= -2mA IOL= -2mA 3 Note
Notes: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0#, CS1#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data Input/Output Capacitance (DQ0-DQ63) Data Input/Output Capacitance (CB0-7)
August 2005 Rev. 1
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT1
Max 95 95 95 18 50 10 95 16 16
Unit pF pF pF pF pF pF pF pF pF
3
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OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, TA = 0C +70C)
WV3DG7266V-D1
PRELIMINARY
Value Parameter Symbol Burst Length = 1 tRC tRC (min) IO = 0mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS# VIH(min), tcc =10ns Input signals are charged one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS# VIH(min), tcc = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tcc = Input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC tRC(min) CKE 0.2V Conditions 7 Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS Icc2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N Active Standby Current in Non-Power Down Mode ICC3NS 1170 75 1080 36 mA 36 360 mA 180 108 mA 108 540 450 mA mA 3 3 3 3 3 10 1080 mA 1 Units Note
Operating Current (Burst mode)
ICC4
1260
1260
1170
mA
1
Refresh Current Self Refresh Current
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 3 Drive ICs.
ICC5 ICC6
2250
2070 54
1980
mA mA
2 3
August 2005 Rev. 1
4
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC OPERATING TEST CONDITIONS
VCC = 3.3v, 0C - 70C Parameter AC input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tR/tF = 1/1 1.4 See Fig. 2
WV3DG7266V-D1
PRELIMINARY
Unit V V ns V
DC OUTPUT LOAD CIRCUIT
AC OUTPUT LOAD CIRCUIT
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA
50 Output Z0 = 50 50pF
OPERATING AC PARAMETER
Parameter Row active to row active delay RAS# to CAS# delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 7 15 15 15 45 60 Version 75 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 Unit 10 20 20 20 50 70 ns ns ns ns us ns CLK -- CLK CLK CLK ea Note 1 1 1 1 1 2 2 2 3 4
Notes: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
August 2005 Rev. 1
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
OPERATING AC PARAMETERS
7 Parameter CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 Symbol Min CLK cycle time tCC 7.5 7.5 Max 1000 5.4 5.4 3 3 2.5 2.5 1.5 0.8 1 5.4 5.4 3 3 2.5 2.5 1.5 0.8 1 Min 7.5 10 75
WV3DG7266V-D1
PRELIMINARY
10 Unit Max 1000 5.4 6 3 3 3 3 2 1 1 5.4 6 6 6 Min 10 10 Max 1000 6 6 ns 1 Note
CLK to valid output delay
tSAC
ns
1, 2
Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to outpu in Hi-Z
tOH tCH tCL tSS tSH tSLZ
ns ns ns ns ns ns ns
2 3 3 3 3 2
CAS latency=3 CAS latency=2
tSHZ
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
August 2005 Rev. 1
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE DIMENSIONS FOR D1
Ordering Information WV3DG7266V10D1 WV3DG7266V7D1 WV3DG7266V75D1 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3
WV3DG7266V-D1
PRELIMINARY
Height* 31.75 (1.250") 31.75 (1.250") 31.75 (1.250")
NOTES: * Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D1
67.56 (2.66) 63.60 (2.50)
4.00 0.10 (0.16 0.039)
6.35 (0.250) Max 2 - R 2.00 (0.078) Min 3.20 (0.125) Min 4.00 (0.157) Min 1.00 0.10 (0.04 0.0039) 31.75 (1.25)
6.00 (0.24)
1
59
61
143
3.30 (0.13)
23.20 (0.91)
32.80 (1.29) 4.60 (0.18) 2.10 (0.083) 2.50 (0.10)
3.80 (0.15)
2 144
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
August 2005 Rev. 1
7
20.00 (0.79)
2 - 1.80 (0.07)
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
512MB - 2x32Mx72 SDRAM UNBUFFERED, w/PLL
WV3DG7266V-D1
PRELIMINARY
Revision History Rev #
Rev 0 Rev 1
History
Created 1.1 Update functional block diagram
Release Date
4-05 8-05
Status
Preliminary Preliminary
August 2005 Rev. 1
8
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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